Mohit Kashyap — Head
Design at codescriet (code.scriet), SCRIET, CCS University Meerut.
Working on VlSI Technology/ Chip designing Motivated ECE fresher with hands-on VLSI verification using SystemVerilog and UVM. Verified AXI interconnect for multi-master/slave traffic and APB-based SPI controller with full testbenches, scoreboards, and coverage to catch protocol issues early. Also designed a 5-stage pipelined 32-bit RISC-V processor in Verilog. Eager to apply protocol expertise (AXI, APB, SPI) and debugging skills in an entry-level verification role at an ASIC/SoC team.